1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to field effect transistors in complex circuits which may include a memory area, wherein information is stored by controlling charge in a floating body of the transistor.
2. Description of the Related Art
Integrated circuits typically comprise a very high number of circuit elements on a given chip area according to a specified circuit layout, wherein advanced devices may comprise millions of signal nodes that may be formed by using field effect transistors or MOS transistors. In the context of the present disclosure, the terms field effect transistors and MOS transistors are considered as synonyms. Thus, field effect transistors may represent a dominant component of modern semiconductor products, wherein advances in performance and low integration volume are mainly associated with a reduction of size of the basic transistor structures. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips, ASICs (application specific ICs) and the like, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using MOS technology, millions of field effect transistors, i.e., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel near the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the latter aspect renders the reduction of the channel length a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Due to the decreased dimensions of circuit elements, not only the performance of the individual transistor elements may be increased, but also their packing density may be improved, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC). Furthermore, in sophisticated microcontroller devices, an increasing amount of storage capacity may be provided on chip with the CPU core, thereby also significantly enhancing the overall performance of modern computer devices. For example, in typical microcontroller designs, different types of storage devices may be incorporated so as to provide an acceptable compromise between die area consumption and information storage density on the one side versus operating speed on the other side. For instance, fast or temporary buffer memories, so-called cache memories, may be provided in the vicinity of the CPU core, wherein respective cache memories may be designed so as to allow for reduced access times compared to external storage devices. Since a reduced access time for a cache memory may typically be associated with a reduced storage density thereof, the cache memories may be arranged according to a specified memory hierarchy, wherein a level 1 cache memory may represent the memory formed in accordance with the fastest available memory technology. For example, static RAM memories may be formed on the basis of registers, thereby enabling an access time determined by the switching speed of the corresponding transistors in the registers. Typically, a plurality of transistors may be required so as to implement a corresponding static RAM cell. In currently practiced approaches, up to six transistors may typically be used for a single RAM memory cell, thereby significantly reducing the information storage density compared to, for instance, dynamic RAM memories including a storage capacitor in combination with a pass transistor. However, usage of storage capacitors may require a regular refreshing of the charge stored in the capacitor, while writing to and reading from the dynamic RAM memory cell may also require relatively long access times so as to appropriately charge and discharge the storage capacitor. Thus, although a high information storage density is provided, in particular when vertical storage capacitor designs are considered, these memory devices may not be operated with high frequency and, therefore, dynamic RAM memories may typically be used for chip internal memories, for which an increased access time may be acceptable.
Moreover, in view of further enhancing device performance, in particular with respect to individual transistor elements, the SOI (semiconductor- or silicon-on-insulator) architecture has continuously been gaining in importance for manufacturing fast transistors due to their characteristics of a reduced parasitic capacitance of the PN junction, thereby typically allowing higher switching speeds compared to bulk transistors. In SOI transistors, the semiconductor region separating the drain and source regions and accommodating the channel regions, also referred to as the body region, is dielectrically encapsulated. This configuration provides significant advantages, but also gives rise to a plurality of issues. Contrary to the body of planar bulk devices, which is electrically connected to the substrate, and thus applying a specified potential to the substrate, maintaining the body of the bulk transistor at a specified potential, the body of SOI transistors is not connected to a specified reference potential. Hence, the body's potential may usually float due to accumulating charge carriers which may be generated by impact ionization, and the like, thereby leading to a variation of the threshold voltage (Vt) of the transistor, depending on the “switching history” of the transistor, which may also be referred to as hysteresis. The threshold voltage represents the voltage at which a conductive channel forms in the body region between the drain region and the source region of the transistor.
The floating body effect is considered disadvantageous for the operation of regular transistor elements, for instance, in particular, for static RAM memory cells, since the operation dependent threshold voltage variation may result in significant instabilities of the memory cell which may not be tolerable in view of data integrity of the memory cell. Consequently, in conventional SOI devices including memory blocks, the drive current fluctuations associated with the threshold voltage variations are taken into consideration by appropriate design measures in order to provide a sufficiently high drive current range of the SOI transistors in the memory block. However, with respect to increasing information density for memory devices compared to static RAM memories and also compared to dynamic RAM memories, as previously explained, the floating body effect and the variation of the threshold voltage associated therewith may be taken advantage of by using the floating body of an SOI transistor as a charge storage region. In this manner, information may be stored in the transistor itself, thereby no longer requiring a charge storage capacitor as in dynamic RAM cells, while also providing the potential for achieving approximately five times the density of current static RAM memories typically comprising six transistor elements.
Consequently, so-called floating body storage transistors have been developed in which charge may intentionally be accumulated in the body region so as to represent a logic high state or low state, depending on the memory technique.
Hence, the technique of floating body storage transistors is a promising approach for significantly increasing information density in SOI semiconductor devices. It turns out, however, that the implementation of “floating body” transistors in other device architectures, which are not compatible with the SOI configuration, for instance due to overall heat dissipation capabilities and the like, is difficult to achieve. For example, in bulk architectures, the body region of planar transistors is in direct contact with the crystalline substrate material so that the isolation of the body region has to be accomplished on the basis of well implantations, thereby significantly increasing the risk of shorting the source and drain regions. Furthermore, for reduced ground rules of small cell sizes, the short channels lead to high electric fields and, thus, to increased leakage currents, thereby significantly reducing overall performance of the storage transistors and also contributing to significant power consumption.
In view of the situation described above, the present disclosure relates to semiconductor devices and manufacturing techniques in which floating body storage transistors and corresponding memory cells and arrays may be provided on bulk architectures while avoiding, or at least reducing the effects of, one or more of the problems identified above.